📚 MOSFET Operation: Regimes, Small-Signal Model, and Subthreshold Behavior

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🎯 Introduction to MOSFET Operation

Metal-Oxide-Semiconductor Field-Effect Transistors (MOSFETs) are fundamental building blocks of modern electronic devices. Understanding their operational principles, including different working modes, small-signal behavior, and subthreshold characteristics, is crucial in electronics engineering. This guide provides a detailed overview of the physical principles governing the current-voltage relationships within these devices.

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1️⃣ MOSFET Operation Regimes

MOSFETs exhibit distinct operating regimes based on the applied gate-source voltage (VGS) and drain-source voltage (VDS).

1.1 Parabolic Regime

✅ Characteristics:

• Occurs when VDS is increased beyond the ohmic regime, but before saturation.
• As VDS increases, the electric field (Fy) along the channel and the electron drift velocity increase.
• However, the inversion charge density (|Qinv|) decreases from the source to the drain side of the channel.
• This reduction in |Qinv| makes the channel more resistive, as fewer electrons are available for current flow.

📈 IDS vs. VDS Behavior (Figure 7b):

• The increase in IDS with VDS is weaker than in the ohmic regime.
• The IDS-VDS curve follows a parabolic trend.
• The growth of IDS eventually becomes null at the vertex of the parabola, where the derivative of IDS with respect to VDS is zero.
• Figure 7a schematically illustrates the inversion charge profile, showing a decrease in |Qinv| from source to drain.

1.2 Saturation Regime

✅ Onset and Physical Explanation:

• The saturation regime begins when VDS exceeds Vsat_DS.
• Mathematically, some initial formulas might predict a falling trend for current in this range, which is physically incorrect. This inconsistency arises because the Qinv expression used becomes invalid for V > Vsat_DS.
• Figure 8 provides a pictorial view of IDS calculation as the integration of the -Qinv vs. V relation. When VDS reaches Vsat_DS, IDS reaches its maximum (Isat_DS). If Qinv were allowed to become negative beyond Vsat_DS, the integral would decrease, leading to a falling IDS.
• Key Insight: For V > Vsat_DS, Qinv should be approximated as zero because the inversion charge (electrons) cannot change sign.
• As VDS increases, the effective threshold voltage (V'T) at the drain side of the channel rises.
• When VDS = Vsat_DS, V'T at the drain side equals VGS, meaning Qinv becomes zero at the drain side. This condition is known as "pinch-off".
• Figure 9a schematically shows that strong inversion weakens from source to drain and is lost at the drain side (pinch-off).
• Beyond pinch-off (VDS > Vsat_DS), the drain loses electrostatic control over the channel region. The voltage drop across the channel effectively remains constant at Vsat_DS.
• Consequently, Fy and the electron drift velocity in the channel no longer increase with VDS, leading to a constant IDS.
• Figure 9b illustrates that IDS saturates at Isat_DS for VDS > Vsat_DS.

⚠️ Limitations of Gradual-Channel Approximation:

• In the saturation regime, especially near pinch-off, the gradual-channel approximation becomes unreliable.
• A more accurate analysis requires solving the two-dimensional Poisson equation to describe the strong electrostatics.

📚 Dominant Transport Mechanism:

• In the ON-state (ohmic, parabolic, and saturation regimes), electron transport is predominantly by drift.
• IDS is proportional to the inversion charge density (Qinv) and the electric field (Fy) or drift velocity (vd).

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2️⃣ Band Diagram Analysis and Channel Electrostatics

Understanding the band diagrams along the channel (y-direction) and across the channel (x-direction) provides crucial insights into MOSFET operation.

2.1 Voltage and Band Profiles along the Channel (y-direction)

• Figure 11 shows the profile of V (quasi-Fermi level for electrons) along the y-direction for different VDS values, with a constant VGS > VT.

  • All curves pass through (y=0, V=0) and (y=L, V=VDS).

• Ohmic Regime (low VDS):

  • Figure 11: V profile is nearly linear. This is because Qinv is approximately constant along the channel.
  • Figure 12a: The band diagram shows a linear drop of EFn from source to drain. EC and EV at the surface follow this linear trend.
  • The electric field Fy(x=0,y) is constant and equal to -VDS/L.

• Parabolic Regime (increasing VDS):

  • Figure 11: The V profile becomes markedly nonlinear, with a steeper increase closer to the drain side.
  • This nonlinearity arises because |Qinv| significantly decreases towards the drain. To maintain a constant IDS, dV/dy must increase with y to compensate for the reduced Qinv.
  • Figure 12b: EFn drops more strongly near the drain, leading to a more pronounced band bending in that region. Fy(x=0,y) is no longer constant but increases with y.

• Saturation Regime (VDS = Vsat_DS):

  • Figure 11: When VDS reaches Vsat_DS, the V profile becomes so steep at the drain side (y=L) that it approaches a vertical slope. This is due to Qinv approaching zero at pinch-off, requiring dV/dy to become infinite to maintain constant IDS.
  • Figure 12c: This translates to a vertical drop of EFn and the energy bands at y=L. Fy(x=0,y=L) becomes theoretically infinite, indicating the breakdown of the gradual-channel approximation at this point.
  • Figure 13: Illustrates the evolution of the EC profile along the y-direction for increasing VDS. It clearly shows that beyond Vsat_DS, the voltage drop from the source to the pinch-off point remains Vsat_DS, while the additional VDS - Vsat_DS drops between the pinch-off point and the drain.

2.2 Two-Dimensional Electrostatics in Saturation

• Figure 14: For VDS ≫ Vsat_DS, the two-dimensional electrostatic analysis reveals complex behavior.
  • Figure 14a: Shows the band diagram along the y-direction at x=0, similar to Figure 12c but emphasizing the strong bending.
  • Figure 14b: Shows the band diagram along the x-direction at y close to L (drain side). It reveals a "field reversal" near the semiconductor surface, where the maximum electron concentration detaches from the surface and moves deeper into the semiconductor. This is due to strong horizontal electric fields from the drain n+ region overwhelming the gate's vertical electrostatic control.

2.3 Channel Length Modulation

✅ Effect:

• When VDS > Vsat_DS, the pinch-off point shifts slightly from the drain edge towards the source.
• This effectively reduces the length of the channel region where strong inversion holds, known as "channel-length modulation".
• Figure 19a schematically depicts this shift, showing an effective channel length L' = L - ΔL.

📈 Impact on IDS (Figure 19b):

• Using L' instead of L in the Isat_DS formula shows that IDS slightly increases with VDS beyond saturation.
• IDS ≈ Isat_DS * (1 + (VDS - Vsat_DS) / (L * Fp)), where Fp is a proportionality constant.
• Figure 19b shows this slight linear increase in IDS in the saturation regime, which is a more accurate description than a perfectly flat saturation curve.

📚 Output Resistance (r0):

• The small-signal output resistance (r0) is the reciprocal of the output conductance (gD) in saturation.
• r0 ≈ LFp / Isat_DS.
• r0 is directly proportional to L and inversely proportional to Isat_DS.
• The extrapolation of the linear IDS trends at different VGS values in saturation often cross the voltage axis at approximately the same VDS, known as the "Early voltage" (analogous to BJTs).

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3️⃣ Small-Signal Model and Key Performance Parameters

MOSFETs are nonlinear devices. A small-signal (linearized) model around a bias point is essential for circuit analysis and device characterization. Figure 16 illustrates the basic intrinsic elements of this model.

3.1 Small-Signal Transconductance (gm)

📚 Definition: gm = ∂IDS/∂VGS

• Measures how a small change in gate voltage affects the drain current.

✅ Formulas:

• Ohmic/Parabolic Regime (VDS ≤ Vsat_DS): gm = µnCox (W/L) VDS
• Saturation Regime (VDS ≥ Vsat_DS): gm = µnCox (W/L) (VGS - VT) / m

📈 Dependence on VDS (Figure 17a):

• Figure 17a shows gm increasing linearly with VDS in the ohmic/parabolic regime.
• In the saturation regime, gm becomes constant with VDS (for a given VGS).
• gm increases with VGS as a parameter.

3.2 Small-Signal Output Conductance (gD)

📚 Definition: gD = ∂IDS/∂VDS

• Measures how a small change in drain voltage affects the drain current.

✅ Formulas:

• Ohmic/Parabolic Regime (VDS ≤ Vsat_DS): gD = µnCox (W/L) [(VGS - VT) - mVDS]
• Saturation Regime (VDS ≥ Vsat_DS): gD = 0 (first-order approximation, refined by channel length modulation)

📈 Dependence on VDS (Figure 17b):

• Figure 17b shows gD decreasing linearly with VDS in the ohmic/parabolic regime.
• In the saturation regime, gD ideally becomes zero (infinite output resistance), though channel length modulation introduces a small non-zero gD.
• gD increases with VGS as a parameter.

3.3 Small-Signal Capacitances

✅ Purpose: Account for the change in inversion layer charge (Qc) due to VGS and VDS variations.

📚 Total Inversion Charge (Qc):

• Qc = ∫ Qinv(y) dy (integrated over channel length L)
• General ON-state: Qc = -WLCox * [ (m²VDS² + 3(VGS-VT)² - 3mVDS(VGS-VT)) / (2(VGS-VT) - mVDS) ]
• Ohmic Regime: Qc ≈ -WLCox(VGS - VT) (Qc equals Qinv multiplied by channel area)
• Saturation Regime: Qc ≈ -(2/3)WLCox(VGS - VT) (Qc is 2/3 of the ohmic value)

✅ Key Capacitances:

• Gate Capacitance (C'G): C'G = -∂Qc/∂VGS
• Drain Capacitance (CD): CD = ∂Qc/∂VDS
• These are related to the model's Gate-to-Source Capacitance (CGS) and Gate-to-Drain Capacitance (CGD):
  • C'G = CGS + CGD
  • CD = CGD

✅ Approximations for CGS and CGD:

• Ohmic Regime: CGS ≈ (1/2)WLCox, CGD ≈ (1/2)WLCox
• Saturation Regime: CGS ≈ (2/3)WLCox, CGD ≈ 0 (due to pinch-off)

⚠️ Important Note: These are intrinsic capacitances. Extrinsic (parasitic) contributions (e.g., overlap and fringing capacitances) are also significant, especially when intrinsic values are small (like CGD in saturation).

3.4 Transit Time (ttr)

📚 Definition: ttr is the time it takes for electrons to travel from the source to the drain.

• ttr = ∫ (1/vd) dy (integrated over channel length L)

✅ Calculation (Charge-Control Model):

• ttr = -∂Qc/∂IDS = -(∂Qc/∂VGS) / (∂IDS/∂VGS) = C'G / gm

✅ Formulas:

• Ohmic Regime: ttr ≈ L² / (µnVDS)
• Saturation Regime: ttr ≈ (2/3)L² / (µnVsat_DS)

📈 Dependence on VDS (Figure 18):

• Figure 18 shows ttr decreasing as VDS increases in the ohmic/parabolic regime, then becoming constant in saturation.
• ttr is directly proportional to L² and inversely proportional to the voltage drop across the channel.

💡 Relation to Cut-off Frequency (ft):

• ft = gm / (2π(CGS + CGD)) = gm / (2πC'G) = 1 / (2πttr)
• A shorter ttr leads to a higher ft, indicating faster device performance.

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4️⃣ Subthreshold Regime and Parametric Influences

4.1 Subthreshold Regime

✅ Characteristics:

• Occurs when VGS is below the threshold voltage (VT).
• The device is nominally "OFF," but a small subthreshold current still flows.
• Vs (surface potential) is not a function of y.

📚 Dominant Transport Mechanism:

• In contrast to the ON-state, electron transport in the subthreshold regime is primarily by diffusion.
• IDS is proportional to the spatial derivative of Qinv in the y-direction.
• Qinv decreases linearly from source to drain, and EFn decreases logarithmically along the channel.

📈 IDS vs. VGS Behavior (Figure 22):

• IDS exhibits an exponential dependence on VGS.
• Figure 22 (semilogarithmic plot) shows a straight-line behavior for IDS vs. VGS in this regime.
• IDS is almost independent of VDS if VDS is greater than a few kT/q (because Qinv at the drain becomes negligible).

📚 Subthreshold Slope (STS):

• Definition: STS = (∂log10 IDS / ∂VGS)^-1, measured in mV/decade.
• Quantifies how effectively VGS can turn the transistor ON/OFF.
• A lower STS means a steeper slope in the semilog plot, indicating more efficient switching.
• Formula: STS = (kT / q ln(10)) * m
• Influencing Factors: Temperature (T) and the body effect parameter 'm'.
• Theoretical Minimum: 60 mV/decade at room temperature (when m=1, representing perfect gate control). Typical values are 70-90 mV/decade.

📈 Current Flattening (Figure 23b):

• At very low VGS (approaching or below VFB), IDS tends to flatten and saturate.
• This is because Vs loses its linear dependence on VGS and becomes logarithmically dependent in the accumulation regime.
• Figure 23a illustrates carrier generation phenomena in the channel.
• Figure 23b shows that generation-recombination processes (e.g., Gate-Induced Drain Leakage (GIDL) current at high VDS and very low VGS) can introduce a current floor, preventing IDS from dropping indefinitely.

4.2 Body Effect

✅ Impact of Bulk Voltage (VBS):

• When a voltage VBS (typically negative) is applied to the bulk contact, it affects device operation.
• Figure 20a shows the real bias scheme with VBS.
• Figure 20b shows an equivalent bias scheme with a grounded bulk, where VGS is replaced by VGS - VBS.
• The primary impact is a change in the threshold voltage, denoted as V'T.

📚 Corrected Threshold Voltage (V'T):

• V'T = VFB + 2|ϕB| + (√(2ϵSiqNa(2|ϕB| - VBS))) / Cox
• This V'T replaces VT in the IDS equations for all regimes.

📈 V'T Dependence on VBS (Figure 21):

• Figure 21 shows that a negative VBS increases V'T.
• The sensitivity of V'T to VBS is given by dV'T / d(-VBS) = Cdep / Cox = m - 1.
• Reducing 'm' (by decreasing tox or Na) reduces the body effect sensitivity.

4.3 Parametric Influences on Device Transcharacteristic

The design parameters and operating conditions significantly affect the MOSFET's IDS-VGS transcharacteristic.

4.3.1 Impact of Oxide Thickness (tox) and Substrate Doping (Na)

✅ Qualitative Effect:

• Reducing tox brings the gate closer to the substrate, improving electrostatic control.
• Reducing Na means less charge needs to be exposed to bend the bands, also improving gate control.
• Both lead to a lower 'm' value, which is beneficial.

📈 Impact on IDS-VGS (Figure 24):

• Figure 24a (Decreased tox): Leads to improved STS (steeper slope), decreased VT, and increased IDS across all regimes.
• Figure 24b (Decreased Na): Similar effects: improved STS, decreased VT, and increased IDS.
• These improvements make it easier for the gate to turn the transistor ON/OFF and achieve higher IDS for the same VGS.

4.3.2 Impact of Temperature (T)

✅ Combined Effects: Temperature affects STS, VT, and electron mobility (µn).

📈 Impact on IDS-VGS (Figure 25):

• Figure 25a (Semilog plot):
  • STS increases with T (flatter slope) due to the kT/q term in its formula.
  • VT decreases with T.
  • The combined effect leads to higher IDS in the subthreshold regime at higher temperatures.
• Figure 25b (Linear plot):
  • Electron mobility (µn) decreases with increasing T (due to phonon scattering).
  • This reduction in µn causes the slope of the IDS-VGS curve in the ON-state to decrease at higher temperatures.
  • Therefore, while IDS increases with T in subthreshold, it may decrease at higher temperatures in the strong ON-state.

4.3.3 Impact of Fixed Oxide Charge and Interface States

✅ Defects and Their Effects:

• Fixed Oxide Charge: Charges within the oxide layer that are not affected by device bias.
  • Figure 26a: Causes a rigid shift of the IDS-VGS curve along the VGS axis. This shift can be compensated by adjusting VGS.
• Interface States: Charge traps at the semiconductor/oxide interface, whose charge state changes with VGS.
  • Figure 26b: Stretches the IDS-VGS transcharacteristic, leading to an increase in the STS (poorer switching).
  • For low VGS, positive interface charge increases IDS. For high VGS, negative interface charge decreases IDS.
  • The VGS value where IDS is unaffected corresponds to the neutral charge condition of the interface states (approximately mid-gap voltage).
  • These defects can degrade device reliability and performance over time.

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