This study material is compiled from a lecture audio transcript and a PDF/PowerPoint text on advanced MOS capacitor behavior.

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📚 Advanced MOS Capacitor Behavior: A Comprehensive Study Guide

💡 Introduction

This study guide provides an in-depth look into the advanced operating principles of Metal-Oxide-Semiconductor (MOS) capacitors. We will explore various conditions and structural modifications that influence their behavior, from deep-depletion states to the innovative MOS capacitor with a ring structure, the analysis of split C-V curves, and the effects of non-ideal factors like fixed oxide charge, interface states, and polysilicon gates. The goal is to clarify these complex topics and enhance your understanding of MOS capacitor dynamics.

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1️⃣ Deep-Depletion Regime

📚 Definition & Scenario

In standard MOS capacitor discussions, it's often assumed that the bias voltage (VG) is applied long enough for the device to reach a stationary electrostatic condition. However, a critical scenario arises when the bias voltage undergoes rapid, large-signal transitions, especially those involving a change in the electron concentration within the inversion layer. Since this concentration cannot change instantaneously, the electrostatic arrangement immediately after the VG transition relies solely on the charge change in the depletion layer.

✅ Key Characteristics

• Non-Equilibrium Condition: The substrate is driven into a non-equilibrium state directly by the applied bias.
• Rapid VG Increase: When VG rapidly increases from 0 (depletion) to a value above the threshold voltage (VT).
• Depletion Layer Extension: The depletion layer extends significantly beyond its maximum equilibrium width (Wmax_d).
• Increased Vs: The voltage across the depletion layer (Vs) rises above 2|ϕB|.
• Fermi Level Shift: The electron quasi-Fermi level (EFn) shifts below the hole quasi-Fermi level (EFp) to maintain the electron concentration.
• Transient Nature: This condition is temporary. Generation processes eventually create enough electrons to return the substrate to thermodynamic equilibrium, causing EFn to move upwards and Wd to decrease.

📊 Band Diagram (Figure 12)

Figure 12 illustrates the band diagram of an MOS capacitor under a deep-depletion condition.

• Vertical Axis: Energy in electron volts (eV).
• Horizontal Axis: Position in nanometers (nm), showing the gate, oxide (ox), and semiconductor regions.
• Key Features:
  • EC (Conduction Band Edge) & EV (Valence Band Edge): Show significant bending, indicating a strong electric field.
  • Ei (Intrinsic Fermi Level): Also bends, reflecting the potential variation.
  • EFp (Hole Quasi-Fermi Level): Remains relatively flat in the bulk, indicating equilibrium for holes.
  • EFn (Electron Quasi-Fermi Level): Is significantly lower than EFp, especially near the surface, highlighting the non-equilibrium state for electrons. The vertical separation between EFn and EFp (qVs) is larger than in equilibrium, indicating a higher Vs.
  • Depletion Layer: Visually, the region where the bands bend significantly is wider than in typical strong-inversion, confirming Wd > Wmax_d.
  • Vs: The voltage drop across the depletion layer is clearly larger than 2|ϕB|, as indicated by the band bending.

📈 Impact on C-V Curve

The deep-depletion regime leads to a distinct C-V curve.

• If a high-frequency small-signal dVG is superimposed while the device is in deep-depletion, the substrate capacitance (Cs) becomes ϵSi/Wd.
• Since Wd > Wmax_d, Cs is smaller than ϵSi/Wmax_d (the value for strong-inversion at high frequency).
• Consequently, the total gate capacitance (CG) is lower than its high-frequency strong-inversion value.
• CG further decreases as the large-signal VG increases, because Wd increases with VG.
• This results in a "deep-depletion C-V curve" (as shown in Figure 10, not provided here but referenced), which follows the low/high-frequency curves in accumulation, depletion, and weak-inversion, but deviates below them above VT, continuing to decrease with increasing VG.

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2️⃣ MOS Capacitor with Ring

⚠️ Limitations of Traditional MOS Capacitors

In basic MOS structures, low-frequency operation relies on generation/recombination processes to change the electron concentration in the inversion layer. These processes are inherently slow, limiting the corner frequency (separating low-frequency from high-frequency regimes) to just a few Hz. While impractical solutions like heating or illumination can increase this, the fundamental structure restricts significant frequency performance improvements.

💡 Introduction of the Ring Contact

To overcome these limitations, the MOS capacitor structure can be modified to avoid reliance on slow generation/recombination processes for inversion layer electron concentration changes.

• Solution: Integrate an ohmic n-type contact that can rapidly supply or remove electrons at the silicon surface.
• Structure: A typical solution is a contacted n+ region running along the perimeter of the gate.
• Nomenclature: This structure is called an "MOS capacitor with ring," and the contact to the n+ region is the "ring contact."
• Device Type: This modification makes the device at least two-dimensional (2-D) with three terminals, also known as a "three-terminal MOS capacitor" or "gated-diode."

🔬 Schematic Structure (Figure 13)

Figure 13 shows the schematic structure of an MOS capacitor with a ring.

• (a) Vertical Cross-section: Depicts the gate, dielectric, and the p-doped semiconductor substrate. Crucially, it shows the n+ ring regions flanking the gate, providing a direct path for electrons to/from the inversion layer.
• (b) Top View: Illustrates how the n+ region forms a ring wrapped around the gate, emphasizing the perimeter contact.

✅ Operating Principle

• Alignment: Proper operation requires good alignment between the n+ region and the gate edges.
• Rapid Electron Flow: A change in gate voltage (VG) creates a quick and strong flow of electrons between the semiconductor region under the gate and the n+ region.
• EFn Gradient: For example, an increase in VG shifts EFn downwards under the gate. Since the n+ region's EFn is not under gate control, a gradient of EFn forms parallel to the silicon surface.
• Modulation: This gradient drives electrons from the n+ region to the area under the gate, reducing the electrostatic potential and shifting EFn upwards. Conversely, a decrease in VG causes electrons to flow from under the gate to the n+ region.
• Frequency Improvement: This mechanism largely increases the low-frequency operation limit. Electron concentration modulation no longer waits for slow generation/recombination but relies on faster electron transit times.
• Extended Low-Frequency Regime: This solution allows extending the low-frequency regime up to hundreds of KHz or MHz, even for typical capacitor areas.

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3️⃣ Split C-V Plot

💡 Enhanced Characterization

The ring contact not only improves frequency response but also offers new ways to investigate device physics and parameters.

🔬 Methodology (Figure 14)

One key possibility is to independently measure the current through the ring and bulk contacts while the gate voltage (VG) is varied over time.

• Assumption: Negligible generation/recombination processes.
• Electron Change (dQn): The ring current directly relates to the change in electron amount (dQn = dQinv) in the inversion layer.
• Hole Change (dQp): The bulk current relates to the change in hole amount (dQp) in the substrate.
• Direct Qinv Evaluation: This allows direct evaluation of the inversion layer charge (Qinv) as a function of VG, crucial for analyzing current transport and electron mobility in MOS transistors.

Figure 14 illustrates the connections for obtaining split C-V curves.

• Gate (VG+dVG): The gate receives both a DC bias and a small-signal AC perturbation.
• Dielectric: Separates the gate from the semiconductor.
• n+ Ring: Connected to measure dQn (electron current).
• p-doped Semiconductor Substrate: Connected to measure dQp (hole current).

📊 Split Capacitance Components

To analyze the electrostatics more deeply, the total gate capacitance (CG) is split into two contributions:

• CG,n: From the modulation of electron concentration.
  • Calculated as: CG,n = -dQn/dVG (where dQn = dQinv).
  • Derived from the ring current.
• CG,p: From the modulation of hole concentration.
  • Calculated as: CG,p = -dQp/dVG.
  • Derived from the bulk current.
• Total Capacitance: CG = CG,n + CG,p.

📈 Split C-V Plot (Figure 15)

Figure 15 shows a "split C-V plot," illustrating the dependence of CG,n and CG,p on the bias voltage VG for a low-frequency small-signal dVG.

• Vertical Axis: Capacitance in µF/cm².
• Horizontal Axis: Gate Voltage (VG) in Volts (V).
• Key Features:
  • Accumulation (VG << VT):
    • CG,n ≈ 0 (negligible electron modulation).
    • CG,p traces the falling branch of the C-V curve, as device electrostatics primarily involve hole flow through the bulk contact (dQs ≈ dQp).
  • Strong-Inversion (VG >> VT):
    • CG,p drops to 0 (negligible hole modulation).
    • CG,n traces the rising branch of the C-V curve, as substrate charge modulation mainly arises from electron concentration changes (dQs ≈ dQn).
  • Near Threshold (VG ≈ VT):
    • Both electron and hole concentration modulations are relevant.
    • CG is the sum of CG,n and CG,p.
    • At VG = VT, dQn and dQp are identical, so CG,n = CG,p.
  • Cox: The oxide capacitance, representing the maximum capacitance.
• Qinv Evaluation: Integrating the CG,n curve along the VG axis directly provides Qinv as a function of VG.

🔬 Small-Signal Model (Figure 16)

While CG = CG,n + CG,p, the typical small-signal model for an MOS capacitor with a ring is structured differently to reflect its physical layout and leverage electrostatic results.

• Model: The device is represented as the oxide capacitance (Cox) in series with the parallel combination of two substrate capacitances: Cs,n and Cs,p.
• Cs,n: Contribution to substrate capacitance from electron concentration modulation (Cs,n = -dQn/dVs).
• Cs,p: Contribution to substrate capacitance from hole concentration modulation (Cs,p = -dQp/dVs).
• Equations: CG,n and CG,p can be calculated from this model:
  • CG,n = (Cox * Cs,n) / (Cox + Cs,n + Cs,p)
  • CG,p = (Cox * Cs,p) / (Cox + Cs,n + Cs,p)

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4️⃣ Ring Bias Effects on Electrostatics (VR > 0)

💡 Non-Grounded Ring/Bulk Contacts

Previously, the ring and bulk contacts were assumed to be grounded. However, applying a voltage (VR) between the ring and bulk contacts introduces significant changes in device operation and electrostatics. We focus on positive VR to avoid forward biasing the p-n junction formed by the n+ ring and bulk.

📊 Band Diagrams with Ring Bias (Figure 17)

Figure 17 presents band diagrams along the vertical direction (center of gate) and horizontal direction (silicon surface) for different VG and VR values. This detailed analysis helps understand the impact of VR.

• Case 1: VG = VR = 0

  • (a) Vertical: Device in thermodynamic equilibrium. Band bending due to work-function difference between gate and bulk, creating a depletion layer under the gate. EF is constant throughout.
  • (b) Horizontal: EC-EF separation is constant under the gate, decreasing as it approaches the n+ region where EC-EF is very small due to high doping.

• Case 2: VG = VT, VR = 0

  • (c) Vertical: Still thermodynamic equilibrium. VG = VT brings the MOS system to the onset of strong-inversion. Vs = 2|ϕB|. EC-EF separation at the surface is small, similar to EF-EV in the bulk.
  • (d) Horizontal: Weak band bending, indicating uniform conditions under the gate.

• Case 3: VG = 0, VR > 0

  • (e) Vertical: Positive VR perturbs equilibrium, separating EFn and EFp. EFn is below EFp. EFn is nearly constant in the n+ region and depletion layer, then grows towards EFp in the bulk. EFp is flat in the bulk and depletion layer, dropping only in the n+ ring. No change in vertical band bending compared to VR=0 because electron concentration is negligible for electrostatics.
  • (f) Horizontal: Positive VR causes a stronger drop in bands when approaching the n+ region, as bands maintain separation from EFn in the quasi-neutral n+ region. EFn is nearly flat horizontally, preventing significant electron flow due to device symmetry.

• Case 4: VG = VT, VR > 0

  • (g) Vertical: Higher VG (VT) increases the vertical voltage drop. EC-EFp at the surface equals EFp-EV in the bulk. However, due to positive VR, EFn is still below EFp, preventing strong-inversion.
  • (h) Horizontal: A significant band drop remains from the region under the gate to the n+ ring, indicating that strong-inversion is not yet achieved.

• Case 5: VG = V'T, VR > 0

  • (i) Vertical: To reach strong-inversion with positive VR, EC at the surface must move further down until its distance from EFn equals EFp-EV in the bulk. This requires Vs = 2|ϕB| + VR. This also means the depletion layer widens beyond Wmax_d, and Vox increases. Consequently, the new threshold voltage V'T is higher than VT.
  • (l) Horizontal: With EC and EFn in close proximity at the surface, the horizontal band bending becomes very weak, similar to the equilibrium strong-inversion case (Figure 17d).

📈 Threshold Voltage Shift (V'T)

The application of a positive VR delays the onset of strong-inversion along the VG axis, prolonging depletion and weak-inversion regimes.

• General Relation: VG - VFB = Vs + Vox
• Conditions at V'T: Vs = 2|ϕB| + VR and Vox = (2ϵSiqNa(2|ϕB| + VR)) / Cox
• V'T Expression: V'T = VFB + 2|ϕB| + VR + (2ϵSiqNa(2|ϕB| + VR)) / Cox
• Simplified V'T: V'T = VT + VR + √[2ϵSiqNa * (√(2|ϕB| + VR) - √(2|ϕB|))] / Cox
  • This shows V'T is not simply VT + VR, but includes an additional term due to the increased depletion layer charge and corresponding Vox.

📈 Vs vs. VG Plot (Figure 18)

Figure 18 shows the total voltage drop over the substrate (Vs) as a function of applied gate voltage (VG), with ring voltage (VR) as a parameter.

• Vertical Axis: Vs in Volts (V).
• Horizontal Axis: VG in Volts (V).
• Key Observations:
  • Accumulation, Depletion, Weak-Inversion: VR does not modify the Vs vs. VG plot in these regimes. Electron concentration is negligible, so its reduction by VR (and EFn lowering) doesn't affect band profile.
  • Strong-Inversion Onset Shift: Increasing VR shifts the onset of strong-inversion to higher VG values (from VT to V'T).
  • Increased Vs Saturation: For VG > V'T, Vs saturates at 2|ϕB| + VR (instead of 2|ϕB| for VR=0). This prolongs the depletion/weak-inversion trend, allowing Vs to reach values higher than 2|ϕB|.
  • Points A, B, C, D: These points illustrate how Vs changes with VR for a given VG, especially in strong-inversion.

📈 Vs vs. VR Plot (Figure 19)

Figure 19 illustrates Vs as a function of VR for two constant VG values (VG,1 < VT and VG,2 > VT).

• Vertical Axis: Vs in Volts (V).
• Horizontal Axis: VR in Volts (V).
• Key Observations:
  • VG = VG,1 (< VT): Vs remains constant regardless of VR (point A in Figure 18). This is because the device is in depletion/weak-inversion, where electron concentration is negligible for electrostatics.
  • VG = VG,2 (> VT):
    • Initially, Vs grows linearly with VR, changing from 2|ϕB| to 2|ϕB| + VR. This occurs as long as the device remains in strong-inversion (points B and C in Figure 18). The increase in VR lowers EFn, reducing surface electron concentration, which in turn increases Vs to maintain strong-inversion (EC-EFn separation constant).
    • Once V'T (which increases with VR) exceeds VG,2, the device transitions out of strong-inversion into weak-inversion/depletion. At this point, further increases in VR no longer affect Vs (point D in Figure 18), as the electron charge becomes negligible for electrostatics.

📚 Inversion Charge (Qinv)

The charge in the inversion layer (Qinv) can be calculated:

• Qinv = Qs - Qdep = Qs + 2ϵSiqNa(2|ϕB| + VR)
• Qinv = -Cox(VG - V'T)
• This equation shows Qinv depends linearly on both VG and V'T. An increase in VR (and thus V'T) leads to a reduction in |Qinv|. If VR is high enough that V'T reaches VG, Qinv becomes zero, indicating the device loses its strong-inversion condition.

📈 C-V Plot with Ring Bias (Figure 20)

Figure 20 shows the impact of VR on the low-frequency C-V curve of an MOS capacitor with a ring.

• Vertical Axis: CG in µF/cm².
• Horizontal Axis: VG in Volts (V).
• Key Observations:
  • Shifted Onset: Increasing VR delays the onset of strong-inversion by increasing VT to V'T.
  • Extended Falling Branch: The falling branch of the C-V curve (depletion and weak-inversion) is extended along the VG axis, reaching lower CG values.
  • Shifted Rising Branch: The rising branch of the curve (strong-inversion) shifts to the right, occurring only when VG reaches V'T.

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5️⃣ Impact of Non-Ideal Effects

⚠️ Real-World Imperfections

Ideal MOS capacitor models assume a perfect insulator and interface. In reality, even high-quality SiO2 and its interface with silicon contain microscopic defects. These defects can increase due to electrical stress and aging, capturing or emitting electrons/holes and becoming electrically charged, significantly affecting device electrostatics and performance.

5.1 Fixed Oxide Charge (Qox)

📚 Definition & Nature

• Origin: Defects within the oxide layer.
• Time Constants: The time constants for these defects to capture/emit electrons/holes are widely distributed (µs to years).
• "Fixed" Assumption: If these time constants are very long compared to the measurement time, the charge introduced by these defects can be considered constant over time and independent of the device's operating point. This is known as "fixed oxide charge."

📊 Band Diagram with Fixed Oxide Charge (Figure 21)

Figure 21 illustrates the effect of fixed oxide charge on the band diagram.

• Vertical Axis: Energy in eV.
• Horizontal Axis: Position in nm (gate, oxide, semiconductor).
• (a) VG = VFB, Qox = 0: Flat-band condition, bands are flat, no charge in substrate or at gate surface.
• (b) VG = VFB, Qox < 0 (Negative): A layer of negative fixed charge (Qox) is introduced in the oxide. This causes the electrostatic potential at the charge location to decrease, creating a peak in the band profile. Positive charge is induced at both the silicon and metal surfaces (e.g., an accumulation layer of holes at the silicon surface). The substrate moves from flat-band to accumulation.
• (c) VG Adjusted to Re-establish Flat-Band: By increasing VG, the Fermi level in the metal (E(m)F) shifts downwards, pulling the oxide bands down. This compensates for Qox, re-establishing the flat-band condition in the substrate.

✅ Impact on Electrostatics

• Rigid Shift: Fixed oxide charge causes a rigid shift of the device's electrostatics along the VG axis.
• Compensating VG: The change in VG (∆VG) needed to compensate for Qox and restore the original substrate condition is given by: ∆VG = - (Qox / ϵox) * x = - Qox / CxG
  • Where x is the distance of the charge layer from the gate, and CxG is the capacitance between the charge layer and the metal.
  • The maximum ∆VG is needed when the charge layer is adjacent to the silicon surface (x = tox).
• Flat-Band/Threshold Voltage Shift: This ∆VG is also referred to as the flat-band voltage shift (∆VFB) or threshold-voltage shift (∆VT).
• Distributed Charge: If Qox is distributed over the oxide thickness (ρox), the formula generalizes to: ∆VG = - (1/ϵox) ∫(from 0 to tox) x * ρox dx

📈 C-V Plot with Fixed Oxide Charge (Figure 22)

Figure 22 shows the C-V plot of an MOS capacitor with and without fixed oxide charge (Qox).

• Vertical Axis: CG in µF/cm².
• Horizontal Axis: VG in Volts (V).
• Key Observations:
  • Qox = 0: The baseline C-V curve.
  • Negative Qox: ∆VG is positive, causing a rightward shift of the entire C-V curve. VG must be increased to compensate for the negative charge.
  • Positive Qox: ∆VG is negative, causing a leftward shift of the entire C-V curve. VG must be decreased to compensate for the positive charge.
• Monitoring Aging: This rigid shift provides a simple way to monitor the build-up of fixed oxide charge over time, indicating device aging.

5.2 Interface States

📚 Definition & Nature

• Location: At the silicon/oxide interface.
• Energy Distribution: Distributed in energy across the semiconductor bandgap.
• Acceptor States: Dominant in the top half of the bandgap; neutral when empty, negatively charged when filled.
• Donor States: Dominant in the bottom half of the bandgap; neutral when filled, positively charged when empty.
• Critical Energy (Eis): Separates acceptor and donor states, close to mid-gap.
• Occupancy: Quickly follows the position of the Fermi level (EF) at the silicon surface (time constants typically not longer than a few µs).

📊 Band Diagram with Interface States (Figure 23)

Figure 23 illustrates which interface states are charged at different conditions.

• Vertical Axis: Energy in eV.
• Horizontal Axis: Position in nm (gate, oxide, semiconductor).
• (a) Flat-Band Condition (VG = VFB):
  • EF at the silicon surface is determined by doping.
  • Donor states above EF are empty and positively charged.
  • Acceptor states below EF are filled and negatively charged.
  • The net charge from interface states (Qis) is typically positive, causing an upward band bending (accumulation of holes) to compensate.
• (b) Strong-Inversion (VG = VT):
  • EF at the silicon surface is near the valence band edge.
  • Acceptor states below EF are filled and negatively charged.
  • Donor states above EF are empty and positively charged.
  • The net Qis can be negative due to filled acceptor states.

✅ Impact on Electrostatics

• Stretching Effect: Unlike fixed oxide charge, interface states do not rigidly shift the electrostatics. Instead, they stretch it along the VG axis.
• Variable ∆VG: The compensating ∆VG is not constant because Qis is a function of the substrate's operating point (i.e., the position of EF at the surface).
  • For VG values where EF is lower than Eis, ∆VG is negative.
  • For VG values where EF is higher than Eis, ∆VG is positive.
• Compensating VG: The ∆VG needed to recover the same band bending is given by: ∆VG = - Qis / Cox (where Qis is the charge density from interface states at the silicon surface).
• Contribution to Capacitance: Interface states also contribute to the substrate capacitance (Cs) because their occupancy changes when a small-signal dVG is applied. This contribution depends on the small-signal frequency relative to the interface state occupancy time constants. At low enough frequencies, interface states can significantly modulate their filling, increasing CG.

📈 C-V Plot with Interface States (Figure 24)

Figure 24 shows the C-V plot of an MOS capacitor with and without interface states.

• Vertical Axis: CG in µF/cm².
• Horizontal Axis: VG in Volts (V).
• Key Observations:
  • Qis = 0: The ideal C-V curve.
  • With Interface States: The C-V curve is stretched along the VG axis. The slope of the transition region (from depletion to strong-inversion) becomes less steep, and the curve appears broadened. This is because different VG values are needed to achieve the same electrostatic condition in the substrate due to the varying charge of interface states.

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6️⃣ Polysilicon Gate

📚 Historical Context & Advantages

While metal gates are now mainstream, polysilicon gates were crucial for the success of CMOS technology for decades.

• Self-Aligned Process: This was the most significant advantage. Polysilicon allowed for a "self-aligned" (or "gate-first") process flow, unlike aluminum which was limited to "nonself-aligned" (or "gate-last") processes.

🔬 Self-Aligned vs. Non-Self-Aligned Process (Figure 25)

Figure 25 schematically compares the two integration schemes.

• (a) Non-Self-Aligned (Gate-Last) Process:
  1. p-doped substrate (a1).
  2. n+ regions (source/drain or ring) are created first (a2).
  3. Oxide and gate material are deposited (a3).
  4. Gate is patterned (a4).
  • Problem: Alignment between the gate and n+ regions relies solely on process accuracy. This leads to unavoidable overlap or distance, causing parasitic capacitances or poor electron supply.
• (b) Self-Aligned (Gate-First) Process:
  1. p-doped substrate (b1).
  2. Oxide and gate are deposited (b2).
  3. Gate is patterned (b3).
  4. The gate acts as a mask for n+ implantation, creating n+ regions perfectly aligned with the gate edges (b4).
  • Benefit: Achieves the best possible alignment, minimizing parasitic effects and improving device performance, especially for scaled devices.

✅ Other Advantages of Polysilicon

• Higher Melting Temperature: Polysilicon (≈1100°C) can withstand the high-temperature thermal annealing required after n+ implantation (to activate dopants and restore crystal quality), unlike aluminum (≈600°C).
• VT Optimization: By changing the doping polarity of the polysilicon gate (n+-doped for n-MOS, p+-doped for p-MOS), the threshold voltage (VT) can be optimized (reduced by almost 1V), which is beneficial for minimizing operating voltage.
  • n+-doped poly-gate (n-MOS): VT ≈ |Qmax_dep|/Cox
  • p+-doped poly-gate (n-MOS): VT ≈ 1V + |Qmax_dep|/Cox
• Reduced Impurity Diffusion: Polysilicon gates reduce the diffusion of impurities into the oxide and silicon surface, maintaining material quality and electrical performance.

⚠️ Drawbacks of Polysilicon Gates

• Lower Free Carrier Concentration: Polysilicon has a lower free carrier density (even when highly doped) compared to metals.
• Non-Negligible Voltage Drop (Vp): To screen an electric field, charge in polysilicon is distributed over a finite length, requiring a non-negligible voltage drop (Vp) within the gate material itself.
• Polysilicon Depletion: When the MOS capacitor is in strong-inversion, the polysilicon gate can be partially depleted at its surface, as shown in Figure 26.

📊 Band Diagram with Polysilicon Gate (Figure 26)

Figure 26 shows the band diagram of an MOS capacitor with a polysilicon gate biased under strong-inversion.

• Vertical Axis: Energy in eV.
• Horizontal Axis: Position in nm (gate, oxide, semiconductor).
• Key Feature: A significant voltage drop (Vp) is observed within the polysilicon gate itself, indicated by the bending of the bands (EC, Ei, EV) within the gate region. This Vp is a portion of the total applied gate voltage.
• Depletion Layer: A depletion layer is formed within the polysilicon gate, similar to the semiconductor, due to the finite carrier concentration.

📈 Impact on C-V Curve (Figure 27)

• Series Capacitance (Cp): The depletion layer in the polysilicon gate introduces a small-signal capacitance (Cp) in series with the oxide and substrate capacitances.
• Total Voltage Drop: VG - VFB = Vs + Vox + Vp
• Total Capacitance: Taking the derivative with respect to Qs: 1/CG = 1/Cs + 1/Cox + 1/Cp
• Effect on CG: While Cp is very large (negligible) in accumulation, depletion, and weak-inversion, it becomes relatively small under strong-inversion.
• Figure 27: The C-V plot for a polysilicon gate MOS capacitor shows that Cp's contribution reduces CG in the strong-inversion regime, making the maximum capacitance slightly lower than Cox.
• Vertical Axis: CG in µF/cm².
• Horizontal Axis: VG in Volts (V).
• Key Observation: The strong-inversion capacitance plateau is slightly lower than Cox, reflecting the series combination with Cp.

🚀 Modern Trends: Return to Metal Gates

• Electrostatic Drawbacks: The voltage loss (Vp) in polysilicon gates became increasingly intolerable with the reduction of operating voltages in advanced CMOS technologies.
• Replacement Gate Schemes: To overcome this, metal gates were reintroduced (starting around 2008) using "replacement gate" schemes. These schemes use a sacrificial gate stack for self-alignment during early integration steps, then replace it with the final gate dielectric and metal gate after high-temperature treatments. This allows combining the benefits of self-alignment with the superior electrical properties of metal gates.